Chip Physical Verification Engineer (Engineer/Staff Engineer)

About the role

MediaTek's Chip Physical Verification team is seeking a qualified Engineer/Staff Engineer to lead full‑chip physical verification sign‑off for advanced SOC designs. The role focuses on ensuring design integrity across multiple verification domains and supporting technology enablement in leading‑edge nodes.

Key responsibilities

• Perform full‑chip physical verification sign‑off covering DRC, LVS, ANT, ERC, ESD, and PERC for tape‑out.
• Collaborate with the Place & Route team to resolve layout integration issues.
• Coordinate with internal IP owners to address IP‑related verification challenges.
• Liaise with the Manufacturing team on DRC concerns.
• Develop automation solutions to improve tape‑out flow efficiency.
• Generate reports on tape‑out verification issues and track resolutions.

Required profile

• Bachelor’s or master’s degree in Electrical/Electronic Engineering or Computer Science.
• Familiarity with the end‑to‑end IC design flow from front‑end to back‑end.
• Strong problem‑solving, analytical, and communication skills.
• Experience with 3D‑IC technologies (e.g., CoWoS, SoIC, EMIB) is a plus.

Required skills

• Proficiency with physical verification tools such as Calibre, ICV, Assura, and Star‑RCXT.
• Script programming experience in Python, TCL, Perl, or C‑shell.
• Strong command of UNIX/Linux environments.