Principal Researcher - Novel DRAM

About the role

Brightecs Innovation Pte. Ltd. (BIP), a Singapore-based semiconductor startup focused on silicon IP for intelligent computing, is looking for a Principal Researcher for Novel DRAM. The role leads research on advanced DRAM architectures and materials, including Si-based 3D DRAM and novel channel oxide materials, within the company's R&D centre, Superam Academy of Semiconductor Research.

Key responsibilities

• Si-based 3D DRAM: lead research and integration of advanced low-resistivity conductive materials for sub-10nm metal lines and interconnects, covering materials screening, property optimisation, process optimisation and HVM readiness.
• Advanced junction formation: define ultra-scaled junction processes, develop low-thermal-budget processes for precise doping profiles and activation in HAR 3D structures, and create novel characterisation technologies for junction profiling.
• 3D architecture and silicide integration: overcome challenges in high aspect ratio structures and develop robust n-type silicide processes with low contact resistance, good step coverage and thermal stability for deep trench/via applications.
• Novel channel oxide materials: develop DRAM array memory architecture, transistor channel materials, device design and performance optimisation, and key process and integration technologies.
• TEG design, peripheral circuits, structural and electrical testing solutions, and materials, process and device simulation.

Required profile

• Master's degree or above (PhD preferred); major in physics, material science and engineering or chemistry.
• 8+ years of DRAM memory development experience, including at least 5 years as an architecture or key technology lead.
• Familiarity with TLC/QLC/PLC multi-bit memory mechanisms, read/write algorithms, ECC and wear leveling.
• Excellent systems thinking and ability to coordinate circuit, device, firmware, verification, testing and product teams.
• Strong technical documentation and technical decision-making communication skills.
• Preferred: in-depth understanding of ECC architecture (BCH/LDPC) and DRAM controller collaboration, familiarity with reliability modelling (TDDB, HCI, RTN), and publication of DRAM papers at international conferences such as ISSCC, VLSI or IMW.