RTL Design Engineer - AI Chip Compute Datapaths

About the role

Campus Singapore is looking for an RTL design engineer to build compute blocks and datapaths for its AI chip. Candidates with a digital RTL design background are welcome to apply.

Key responsibilities

• Translate specifications into microarchitecture and synthesizable RTL for AI chip compute datapaths
• Develop SystemVerilog modules: interfaces, pipelines, FSMs and control logic
• Collaborate with verification teams to debug functional, timing and interface issues
• Optimize performance, power and area through synthesis and timing analysis, and maintain design documentation and scripts
• Leverage AI tools to improve engineering workflow efficiency

Required profile

• Bachelor's degree or above in Microelectronics, IC, EE, CS, Automation or a related major
• Solid digital logic foundation: FSM, pipeline, setup/hold time
• Basic knowledge of computer architecture and Linux; able to automate scripts and debug with AI assistance
• Clear logical thinking, good teamwork and focus on design quality and correctness
• Bilingual in Chinese and English
• Preferred: projects or internships on processors or AI accelerators, familiarity with MAC units, floating-point arithmetic, memory or on-chip interconnect, and exposure to synthesis, STA, Lint, formal verification or UVM

Required skills

• Verilog and SystemVerilog, including coding and simulating simple RTL independently
• Preferred: synthesis, STA, Lint, formal verification, UVM and basic LLM compute knowledge

What we offer

• Mentorship from senior hardware engineers through design and RTL reviews
• A hands-on AI chip project, growing from module work to owning microarchitecture and RTL
• Full digital design cycle exposure: design, simulation, synthesis and timing closure
• Growth track toward becoming an independent compute/datapath module designer