ISP RTL Design Engineer

OMNIVISION · Singapour

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🇬🇧 English

Verilog SystemVerilog SystemC High Level Synthesis C++ CMOS Image Sensor

Job description

About the role

We are looking for an ISP RTL Design Engineer to implement image signal processing algorithms in hardware. The role involves translating ISP algorithms into Verilog, SystemVerilog or SystemC, verifying the logic, and optimizing for area and power.

Key responsibilities

Implement ISP algorithms in hardware using Verilog, SystemVerilog and/or SystemC (High Level Synthesis).
Verify ISP‑level and digital system‑level logic to ensure functional correctness.
Optimize designs for reduced gate count and low power consumption.
Collaborate closely with the ISP Algorithm team to drive design activities.

Required profile

Minimum MSEE, BSEE or equivalent engineering degree.
Strong knowledge of RTL design, C/C++ programming and verification.
Excellent debugging and problem‑solving abilities.
Good communication and interpersonal skills.
Result‑oriented mindset and adaptability to change.

Required skills

Verilog
SystemVerilog
SystemC
High Level Synthesis
C / C++ programming
CMOS Image Sensor domain knowledge (preferred)

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Published 13 hours ago

Expires 1 month from now

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OMNIVISION

Singapour

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