Silicon Design Engineer - RTL Integration

About the role

AMD is seeking a Silicon Design Engineer to integrate RTL components from multiple design teams into its next‑generation FPGA and programmable SoC products. The role focuses on building full‑chip RTL connectivity models, verifying architectural intent, and creating custom tools to improve development efficiency and quality.

Key responsibilities

• Develop full‑chip SoC RTL and associated design specification documents.
• Integrate IP components from various development teams.
• Collaborate with architecture, software, and verification groups to ensure RTL quality.
• Run lint and other static verification tools.

Required profile

• Strong passion for modern, complex processor architectures and digital design.
• Excellent communication and teamwork skills across globally distributed teams.
• Analytical problem‑solving ability, self‑starter attitude, and willingness to learn.

Required skills

• Proficient in Verilog/SystemVerilog HDL coding.
• Experience with CAD tools such as VCS, Verdi, Design Compiler, PrimeTime, Spyglass, Lint, Conformal, CDC/RDC tools.
• Understanding of timing constraints for synthesis and static timing analysis at the SoC level.
• Familiarity with Unix/Linux environments and scripting languages (Shell, Perl, Python).
• Experience with revision control systems, e.g., Perforce.
• Background in FPGA and ASIC design flows.