CPU Design Engineer – RTL Integration

About the role

We are looking for a CPU Design Engineer to lead micro‑architecture design and RTL integration of high‑performance processor cores. The role is based in Singapore and will work closely with architecture, verification and backend teams to bring silicon IP from concept to tape‑out.

Key responsibilities

• Define micro‑architecture, document design and specify key CPU modules such as ALU, pipeline control, MMU and cache controller.
• Develop Verilog/SystemVerilog RTL for core modules and ensure coding quality and low‑power compliance.
• Integrate independent IP blocks, perform top‑level wiring, bus‑interface docking and resolve timing, area and power conflicts.
• Collaborate with verification to create test cases, run simulations and debug functional issues.
• Support synthesis, static timing analysis and timing‑closure activities with backend teams to meet PPA targets.
• Participate in pre‑ and post‑tape‑out debugging, including silicon bring‑up and validation.

Required profile

• Master’s degree or higher in Microelectronics, Computer Science, Electronic Engineering or related field.
• Strong theoretical knowledge of CPU architecture, pipelines, out‑of‑order execution, branch prediction and memory hierarchy.
• Experience with RTL integration of large‑scale SoCs or CPU subsystems and familiarity with AMBA AXI/AHB/APB protocols.
• Good scripting abilities (Tcl, Python or Perl) for automation of integration flows.

Required skills

• Verilog / SystemVerilog RTL coding.
• RTL integration and bus protocol implementation (AMBA AXI, AHB, APB).
• Scripting languages: Tcl, Python, Perl.
• Front‑end design flow: logic synthesis, static timing analysis, formal verification, DFT.
• Understanding of low‑power design and code synthesizability.
• Familiarity with RISC‑V or ARM CPU architectures (preferred).