SOC Design Engineer – Front‑End Design

About the role

MaxLinear is looking for a SOC Design Engineer to join its Front‑End Design team. You will work on cutting‑edge wireless connectivity SOCs, creating high‑quality RTL and collaborating with verification and backend groups to bring complex chips to silicon.

Key responsibilities

• Develop digital logic in VHDL/Verilog from specifications, handling multiple clock domains, functional modes and analog interfaces.
• Produce low‑power RTL using standard power intent files (UPF/CPF) and ensure DFT compliance.
• Write FPGA‑friendly RTL, create test‑bench simulations and debug prototypes on FPGA.
• Collaborate with RTL‑to‑netlist and backend teams to resolve design issues and support tape‑out.
• Participate in synthesis, logic‑equivalence checks and optional clock & reset architecture design.

Required profile

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering with a focus on IC design.
• Experience (or academic projects) covering the full SOC design flow for 65 nm to 16 nm technologies.
• Ability to work independently, meet deadlines and communicate effectively in a multicultural team.

Required skills

• VHDL / Verilog RTL coding
• Low‑power design methodologies (UPF, CPF)
• FPGA prototyping and test‑bench simulation
• Design‑for‑test (DFT) concepts
• Synthesis and logic‑equivalence verification
• Understanding of SOC/ARM/AHB bus architectures
• Familiarity with wireless protocols such as GPS, WLAN, BT, NFC, Ethernet (optional)