Senior ASIC Design Engineer

About the role

We are seeking a Senior ASIC Design Engineer to join our fast‑growing team in Singapore. You will play a key part in creating next‑generation AI chips built on a revolutionary architecture, collaborating closely with verification, front‑end, and software groups to deliver high‑quality digital IC solutions.

Key responsibilities

• Develop micro‑architecture and RTL for AI compute subsystems.
• Analyse performance, power and area (PPA) to meet strict cost and energy targets.
• Contribute to RTL design of SoC modules and assist with IP core integration.
• Support chip‑level system tasks such as clock/reset architecture, low‑power techniques, and bus architecture.
• Work with verification and testing teams on module‑level and system‑level validation.
• Help front‑end engineers with netlist delivery and timing issue resolution.
• Provide driver development assistance, debugging support, and technical documentation.

Required profile

• Bachelor’s degree or higher in Electrical Engineering or a related field.
• At least 3 years of experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals.
• Proficiency in Verilog HDL and familiarity with ASIC design flow and EDA tools such as Synopsys and Cadence.
• Good knowledge of CPU and cache architectures, ISA and compiler principles.
• Experience with bus systems, DMA, peripheral interfaces and low‑power design methodologies.

Required skills

• Verilog HDL
• ASIC design flow
• Synopsys tools
• Cadence tools
• CPU and cache architecture
• Instruction set architecture (ISA)
• Compiler principles
• AMBA, AXI, AHB, APB bus protocols
• DMA and peripheral interface design
• Low‑power design techniques
• Synthesis, timing analysis and DFT concepts