Senior Design Engineer

About the role

We are looking for a Senior Design Engineer to lead the development of high‑performance RFIC blocks. You will work closely with cross‑functional teams to translate system requirements into silicon, ensuring technical feasibility and risk mitigation throughout the product lifecycle.

Key responsibilities

• Participate in requirement and specification discussions, identify feasibility and risks.
• Research and develop RF block architectures such as CTLE, VGA, TIA, DRV, and FFE.
• Collaborate with layout engineers on placement and routing, and run iterative post‑layout simulations to optimise performance.
• Produce design reports at each stage to meet milestone quality standards.
• Support chip bring‑up, define test plans, align simulations with measurements, and debug hardware issues.

Required profile

• Master’s degree with 5+ years or Ph.D. with 3+ years of relevant industry experience.
• Proven experience in high‑bandwidth RFIC design on SiGe/CMOS processes.
• Track record of successful silicon validation, tape‑out, and issue localization.
• Ability to guide layout engineers and work effectively under pressure.

Required skills

• RFIC circuit design
• SiGe and CMOS process expertise
• Design of CTLE, VGA, TIA, DRV, and FFE blocks
• Post‑layout simulation and performance optimisation
• Layout placement and routing supervision
• Silicon bring‑up, debugging and tape‑out experience