Silicon Verification Engineer

About the role

We are looking for a motivated Verification Engineer to join AMD’s DDR PHY IP development team. In this entry‑level position you will help verify high‑performance DDR PHY intellectual property that powers data‑center, mobile and automotive SoCs. You will collaborate closely with design and architecture groups to build robust verification environments and ensure silicon success.

Key responsibilities

• Develop and maintain UVM‑based verification environments for DDR PHY IP.
• Write and execute directed and constrained‑random test plans, functional coverage models, and regression runs.
• Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
• Create and maintain verification collateral such as testbenches, checkers, and scoreboards.
• Track functional coverage and ensure full verification closure.
• Contribute automation scripts for regression management and data analysis.

Required profile

• Passionate about digital design with a strong foundation in clocking, timing, state machines and basic analog concepts.
• Detail‑oriented, eager to learn and able to work in a collaborative, fast‑paced environment.
• Excellent analytical, debugging and communication skills.
• Motivated to grow expertise in memory interface technologies.

Required skills

• Academic or internship experience with SystemVerilog and UVM.
• Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium or Mentor Questa.
• Basic understanding of DDR memory protocols and PHY architecture.
• Proficiency in scripting languages (Python, Perl or TCL) for automation.