Senior/Staff 3D Process Integration Engineer

About the role

Bitdeer is seeking a senior-level engineer to lead the definition and integration of 3D process stacks for high-performance computing and AI applications. The role will own the end-to-end workflow from stack architecture through thermal sign-off and tape-out, collaborating with foundries, memory partners and outsourced assembly houses.

Key responsibilities

• Define the WoW stack, TSV/hybrid-bond interfaces, pad pitch, keep-outs and alignment budgets in partnership with the foundry and memory IP partner.
• Generate 3D-aware floorplan inputs, including bump/TSV/HB maps, micro-bump planning and die-to-die interface placement together with the physical design team.
• Establish and close DFM and 3D design rules, conduct design-rule and process-assumption reviews.
• Coordinate thermal and thermal-mechanical (stress/warpage) analyses and feed mitigation strategies back into floorplan, power delivery and stack selection.
• Lead 3D sign-off activities covering thermal, SI/PI across die-to-die interfaces and known-good-stack validation before tape-out.
• Work with DFT to define 3D test strategies, including stacked-die access and compliance with IEEE 1838.
• Manage package and substrate co-design hand-off to OSATs, addressing stack-up, escape routing, assembly flow and yield/reliability considerations.
• Track deliverables and milestones from foundry and memory partners, surface integration risks early and keep the stack plan aligned with the overall schedule.

Required profile

• BS/MS/PhD in Electrical Engineering, Materials Science, Mechanical Engineering or a related discipline.
• 5+ years of experience in 3D-IC, advanced packaging or process integration, with at least one product taken through tape-out and assembly.
• Hands-on expertise with TSV and hybrid bonding and familiarity with wafer-on-wafer, chip-on-wafer or SoIC/CoWoS-class stacking flows.
• Working knowledge of TSMC 3DFabric (SoIC, CoWoS, InFO) or an equivalent 3D ecosystem, including design kits and rule decks.
• Strong understanding of thermal and thermal-mechanical behavior in stacked dies and of SI/PI at die-to-die interfaces.
• Proven ability to coordinate cross-functional interfaces with foundries, memory IP partners and OSATs.

Required skills

• Through-silicon via (TSV) integration
• Hybrid bonding
• 3D stacking flows (wafer-on-wafer, chip-on-wafer, SoIC/CoWoS)
• TSMC 3DFabric ecosystem (SoIC, CoWoS, InFO)
• Thermal analysis
• Thermal-mechanical (stress/warpage) analysis
• Signal integrity (SI) and power integrity (PI) across die-to-die interfaces
• Design for manufacturability (DFM) and design-rule reviews
• Design for test (DFT) for 3D stacks
• OSAT hand-off and package/substrate co-design