SoC Digital Design Engineer – Multimedia Lab

About the role

ByteDance’s Multimedia Lab is building industry‑leading video codec hardware solutions on FPGA and ASIC platforms. We are looking for a SoC Digital Design Engineer to design high‑performance video encoding and processing accelerators that serve billions of users worldwide.

Key responsibilities

• Define and evaluate the architecture of SoC top‑level blocks or subsystems such as NoC, CPU, NPU, ISP, and video codec.
• Write clean, well‑structured RTL code in Verilog/SystemVerilog and maintain design documentation.
• Perform front‑end quality checks including linting and clock‑domain crossing (CDC) analysis.
• Conduct power, performance, and area (PPA) assessments during early design phases.
• Collaborate with algorithm, architecture, software, firmware, and verification teams to deliver scalable hardware solutions.

Required profile

• Strong background in digital hardware design for video or multimedia applications.
• Experience with ASIC/FPGA development flow and verification methodologies.
• Ability to work in a fast‑growing, cross‑functional team and deliver high‑quality results.

Required skills

• Verilog / SystemVerilog
• RTL design and implementation
• SoC architecture (NoC, CPU, NPU, ISP, Codec)
• FPGA and ASIC design flows
• Video codec hardware knowledge
• Lint and CDC analysis
• PPA (Power, Performance, Area) evaluation

What we offer

• Positive team atmosphere and career growth opportunities
• Competitive compensation (SGD 6,500‑13,000 per month)
• Paid leave, meals provided, and access to cutting‑edge video technology