ASIC RTL/SoC Design Engineer (Singapore)

About the role

TetraMem is seeking an experienced ASIC RTL/SoC Design Engineer to lead RTL design, simulation, and verification for its next‑generation AI and in‑memory computing products. The role involves close collaboration with backend, software, and architecture teams to deliver high‑performance silicon.

Key responsibilities

• Lead RTL design, simulation, and verification for TetraMem ASIC/SoC products.
• Integrate and validate IP blocks, ensuring seamless system functionality.
• Perform Power, Performance, and Area (PPA) analysis to optimize trade‑offs.
• Collaborate with the backend team through coding, implementation, and synthesis to achieve successful tape‑out.
• Develop reusable internal IPs for AI and in‑memory computing applications.
• Support post‑silicon testing, diagnose issues, and ensure product quality.
• Mentor junior engineers and contribute to design reviews and cross‑functional discussions.

Required profile

• MS with 5+ years of experience or PhD in Electrical Engineering focusing on RTL/SoC/digital design.
• Strong knowledge of Verilog and SystemVerilog.
• Experience with industry tools such as VCS and Verdi.
• Understanding of pre‑layout and post‑layout simulation flows.
• Familiarity with AMBA APB/AXI protocols and RISC/Arm core architectures.
• Ability to work independently and provide technical leadership in a startup environment.

Required skills

• Verilog
• SystemVerilog
• VCS, Verdi (or equivalent)
• Pre‑layout and post‑layout simulation
• AMBA APB/AXI protocol
• RISC/Arm architecture
• FPGA/ASIC design for image‑processing systems
• SoC architectures (CPU, GPU, accelerators)
• UVM, place‑and‑route, static timing analysis (STA)
• EM/IR/Power analysis