Senior Physical Design Engineer

About the role

Bitdeer is seeking a Senior Physical Design Engineer to lead the physical implementation of high‑speed PCIe IP and subsystems for AI chips. You will own the complete design flow from netlist to GDSII, collaborating closely with circuit design, DFT, and verification teams to deliver silicon‑proven, high‑performance solutions on leading‑edge process nodes.

Key responsibilities

• Own end‑to‑end physical design flow: floorplanning, placement, CTS, routing, STA, physical verification and sign‑off for PCIe controller and PHY blocks.
• Perform timing closure for high‑speed PCIe Gen 4/5/6 interfaces across PVT corners.
• Drive power‑integrity analysis, including IR‑drop and electromigration across the power delivery network.
• Achieve physical verification closure (DRC, LVS, ERC) using Calibre tools.
• Collaborate with RTL and synthesis teams to provide feedback for logic restructuring, improving timing and area.
• Contribute to internal physical‑design methodology, scripts, and flow automation using Perl and Tcl.
• Support tape‑out activities, including final GDS merge, fill insertion, and sign‑off checks.

Required profile

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands‑on physical design experience in advanced TSMC nodes (N6 or below preferred).
• Strong knowledge of PCIe protocol and high‑speed interface physical‑design constraints.
• Extensive CTS experience for high‑speed designs, including skew balancing and multi‑corner closure.
• Proficiency with industry‑standard place‑and‑route and timing sign‑off tools (Cadence Innovus, Synopsys PrimeTime, Tweaker).
• Experience resolving chip‑level DRC/LVS/EMIR issues on advanced nodes.
• Experience in multi‑die packaging (WoW, 2.5D/3D), thermal/IR/EM sign‑off, signal integrity, or DFT‑aware physical design is a plus.
• Proficiency in Python, Perl, Tcl, and Make scripting is a plus.
• Demonstrated tape‑out experience.

Required skills

• PCIe Gen 4/5/6 protocol
• Clock Tree Synthesis (CTS)
• Cadence Innovus
• Synopsys PrimeTime
• Tweaker
• Calibre (DRC/LVS/ERC)
• Python
• Perl
• Tcl
• Make scripting
• TSMC N6 (or smaller) process nodes
• Power‑integrity analysis (IR‑drop, electromigration)