Senior / Staff ASIC Design Engineer (On-Chip Test & Diagnostics)

About the role

This role designs and verifies on-chip test, monitoring and diagnostic IP for analog and mixed-signal failure detection, and integrates it into SoC subsystems. It sits within a cross-functional team of digital, analog and mixed-signal designers, DFT engineers, SoC architects and product/test teams.

Key responsibilities

• Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring and diagnostic IP, and build and verify digital logic blocks such as test controllers, sequencing, sensor/interface control, measurement, data capture and failure detection logic.
• Build clean register and bus-connected interfaces (APB, AHB, AXI-lite) for firmware interaction and subsystem integration.
• Develop testbenches, assertions, checkers and verification environments, and run functional verification for normal, corner, negative and fault-injection scenarios.
• Collaborate with analog and mixed-signal designers on behavioral models, stubs and interface abstractions, and debug RTL and simulation issues with waveform analysis and root-cause investigation.
• Ensure RTL is modular, reusable, timing-aware, synthesis-friendly and scalable across SoC derivatives.
• Integrate the IP into SoC subsystems and system-level test architecture, working with SoC integration and DFT teams on clock/reset, interrupts, status visibility, CDC, reset interactions, timing, low-power and handoff.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field, with 5-7 years of relevant experience.
• Strong hands-on RTL design experience; practical RTL verification, simulation and debugging experience.
• Solid understanding of the ASIC/SoC design flow (coding, simulation, synthesis, integration).
• Experience in complex SoC environments with cross-functional teams.

Required skills

• RTL design in Verilog/SystemVerilog
• Digital design basics: FSM, datapath, bus protocols (AXI/AHB/APB), clock-domain handling, reset strategy and timing
• Preferred: control, monitoring or diagnostic IP for analog/mixed-signal systems, behavioral modeling, scripting or automation for verification