SoC Digital Design Engineer, Multimedia Lab

About the role

Our Multimedia Lab team at ByteDance is building industry‑leading video codec hardware solutions (FPGA and ASIC) to serve billions of users. As a SoC Digital Design Engineer you will design hardware accelerators for advanced video encoding and processing, working alongside experts in algorithm, architecture, software, firmware and verification.

Key responsibilities

• Define and evaluate the architecture of SoC tops or subsystems (NoC, CPU, NPU, ISP, Codec) and conduct PPA (Power, Performance, Area) analysis.
• Write high‑quality RTL code in Verilog/SystemVerilog and maintain design documentation.
• Perform front‑end quality control, including lint checks and CDC verification.
• Collaborate with cross‑functional teams to integrate video codec IP into scalable hardware platforms.

Required profile

• Strong background in video codec hardware design and accelerator development.
• Experience with ASIC/FPGA design flow and SoC architecture.
• Ability to work in a fast‑growing, multidisciplinary team.

Required skills

• Verilog / SystemVerilog
• RTL implementation
• SoC architecture (NoC, CPU, NPU, ISP, Codec)
• PPA evaluation
• Lint and CDC analysis
• FPGA and ASIC design
• Video codec hardware acceleration

What we offer

• Positive team atmosphere and career growth opportunities
• Competitive compensation (SGD 11,250‑22,500 per month)
• Paid leave and meals provided
• Work with cutting‑edge video technologies serving over 100 million users