Foundry Interface Engineer

About the role

Proto, part of Block, is building Bitkey, a self-custody bitcoin wallet, and hardware and software for bitcoin mining. The Foundry Interface Engineer works with foundry partners and third-party vendors as well as internal teams to continuously improve the design of ASICs. Key tasks include partnering with OSAT to review production wafer test data and working with standard cell circuit designers to analyse results and request process fine-tuning from the foundry.

Key responsibilities

• Review and assess foundry silicon data against SPICE and design goals, and compile a SPICE-to-Silicon gap analysis
• Drive foundry partners on CIPs to improve the foundry process and meet technology entitlement and product goals
• Identify device parameter changes with the foundry to enable efficient low-voltage operation
• Work with circuit designers on device improvements for performance and energy efficiency
• Manage foundry PDK and design library collateral with foundry partners and vendors
• Guide internal IP and design teams on using technology attributes such as performance, power, area and cost
• Collaborate with infrastructure, customization, test-chip, methodology, packaging and product test teams on product bring-up and productization
• Analyze and validate production wafer data with test engineers and contribute to binning strategy to maximise parametric yield

Required profile

• 10+ years of post-education experience in FAB/fabless environments, technology definition and bring-up, device/process architecture and NPI
• Experience with foundry design kits, SPICE, DR/DRC evaluation and SPICE-to-Si assessment
• Experience with advanced node device physics (e.g. FinFET/GAA), backside power and product design phases
• Understanding of product KPIs, DTCO and parametric, DLY/PLY analysis and gap closure
• Understanding of low-power techniques (Vmin reduction, power gating, multi-voltage design, clock network optimisation) and layout effects on circuits

Preferred

• Master's or PhD in Electrical Engineering, Physics or a related field (not a substitute for experience)
• Production test development experience
• Familiarity with 3nm and 2nm FinFET nodes, PDK and device models, and standard cell design and layout
• Previous work at semiconductor foundries