IC Layout Engineer

About the role

Broadcom is looking for an IC Layout Engineer responsible for delivering high-quality layouts of Standard Cells, I/O pads and Mixed-Signal IP in advanced processes, within project schedules.

Key responsibilities

• Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
• Manage the schedule and execute layouts from the transistor level up, including cell- and block-level floorplanning.
• Adopt new methodologies, communicate actively across sites and work closely with senior layout engineers.

Required profile

• Bachelor's degree in Electronic Engineering.
• 2 to 3 years of hands-on IC layout experience.
• Quick learner, proactive, team player with good communication and strong problem-solving skills.

Required skills

• Solid grasp of Standard Cell, Memory or Analog/Mixed-Signal layout basics.
• Familiarity with basic ESD/Latch-up layout techniques and transistor-level placement.
• Practical experience with physical verification: DRC, LVS, ERC and antenna checks.
• Basic understanding or exposure to sub-micron or advanced process nodes (e.g. 5nm, 3nm, 2nm, 1.4nm).
• Proficiency with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, antenna, EM/IR analysis).
• Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus.