NAND Design Rule Manager

About the role

Micron is looking for a NAND Design Rule Manager to lead a team supporting both development and large-scale production of advanced 3D NAND technologies. The role is essential for producing accurate design-rule and PDK results, ensuring high quality and keeping strict documentation across R&D and production.

Key responsibilities

• Lead the release of design rules and PDK deliverables, and coordinate DRC waivers, mask definitions and mask reviews for R&D and production.
• Own program execution from kickoff through end-of-life.
• Partner with Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit processes (PHOTO/OPC/CMP) and Quality & Reliability to guide new 3D NAND generations.
• Ensure high-quality Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Work with Yield Improvement, Product Engineering, Defect Analysis and Quality Assurance to identify layout- or database-related process issues and prioritise corrective actions.
• Build and evaluate test structures to generate data for next-generation devices and assess process margin on current technologies.
• Communicate status, risks and resolutions clearly across functions and management levels, and define and track sub-milestones within PDK/DBR/TO schedules.
• Drive continuous improvement in design-rule pathfinding and share AI-enabled enhancements within scope.

Required profile

• PhD in Electrical Engineering, Microelectronics, Physics or Semiconductor Materials Science with 5+ years of relevant experience; or Master's with 8+ years; or Bachelor's with 13+ years in the semiconductor industry (Process Integration, Yield Improvement, Product Engineering, Test Structure Development or Unit Process Development).
• Direct experience with PDK, design rules and layout, including small layout assignments.
• Solid understanding of semiconductor device physics and VLSI silicon processing and integration flow.
• Understanding of 3D NAND process flow and major NAND components (bit-line sensing, word-line driver, data path, analog circuits).
• Familiarity with CAD group interactions, data post-processing and data transfer from built databases to reticles.
• Prior leadership experience in R&D for NAND or other memory technologies is preferred.

Required skills

• CAD software such as Cadence Virtuoso, K2View and Mentor Graphics DRC/RVE, or equivalents.
• Ability to resolve complex issues and communicate clearly under pressure.