Senior C++ Engineer - High Frequency Trading

About the role

The Systematic Platform Execution & Exchange Data (SPEED) team builds the live trading and market-data platforms used by portfolio managers and risk systems, covering latency tiers from sub-100 nanoseconds to milliseconds. As a Senior HFT Developer on SPEED, you will design and build core low-latency components for order entry, market data, exchange simulation, feature extraction and strategy containers, working with system architects and quantitative researchers and providing technical leadership for the HFT platform in the APAC region.

Key responsibilities

• Build low-latency infrastructure for order entry, market data, exchange simulators, feature extraction, strategy containers and other systems.
• Build convenience-layer tools and services to help trading teams onboard at MLP.
• Take part in a follow-the-sun L2 support rotation, troubleshooting production issues in real time.
• Work with the SPEED architect, quantitative researchers and the business to deliver high-ROI solutions aligned with business and platform strategy.
• Provide technical leadership for the low-latency trading platform in the APAC region, own key architectural decisions, set performance and quality standards and mentor less-experienced engineers.
• Liaise with many other MLP teams depending on project focus.

Required profile

• 5+ years with a well-regarded HFT group delivering production-grade, low-latency systems.
• Demonstrated expertise in C++ and Python for production, low-latency systems.
• Experience with HPC grids (scheduling, storage, job management) for research and production workloads.
• Cloud experience (AWS, GCP) is a plus.
• Proven ability to navigate large organizations, build cross-team synergies and influence outcomes.
• High accountability, self-management and demonstrated technical leadership with team-management potential.

Required skills

• Strong understanding of Linux internals, CPU architecture (caches, NUMA, branch prediction) and performance profiling.
• Ultra-low-latency networking (multicast market data, TCP/UDP); kernel-bypass such as DPDK/Onload and custom NIC/FPGA stacks are a plus.
• Strong understanding of the HFT quantitative research pipeline.