Senior DFT Engineer

About the role

Broadcom is looking for a highly motivated Design-for-Test (DFT) Engineer to join its SoC/ASIC DFT development team. The role covers implementing and verifying DFT solutions across complex hierarchical designs, with hands-on DFT insertion and comprehensive DFT verification aimed at first-pass silicon success. The engineer works closely with the physical design team and ATE test teams to build efficient, high-quality test strategies.

Key responsibilities

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs, at block and top levels.
• Perform scan insertion, test point insertion and test compression using SSN or equivalent architectures.
• Validate SSN topology, manage scan chain balancing and clock domain crossings.
• Integrate boundary scan (IEEE 1149.x) and other test access mechanisms.
• Generate and analyze ATPG patterns for stuck-at, transition and path delay faults.
• Perform DFT verification, including Verilog and gate-level simulation.
• Work with cross-functional teams to resolve DFT and testing timing issues.
• Collaborate with ATE engineers to prepare and validate STIL/WGL timing and pattern files.
• Support silicon bring-up and production test debugging through diagnostics and failure analysis.

Required profile

• Bachelor's or master's degree in electrical engineering, computer engineering or a related field.
• At least 3 years of experience in DFT design and verification (5+ years preferred for a senior role).
• Strong understanding of scan-based test architectures, test compression and hierarchical DFT.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.

Required skills

• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis and gate-level DFT verification.
• Scripting in TCL, Perl or Python for DFT automation.