Senior ISP RTL Design Manager

About the role

This role leads the implementation of ISP algorithms into hardware, defines the ISP hardware architecture and drives RTL design activities across sites. It also involves leading, supervising and mentoring a team of RTL design engineers.

Key responsibilities

• Implement ISP algorithms into hardware using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define the ISP hardware architecture based on product features and performance requirements, including gate count and power estimation
• Verify logic at ISP level and digital system level
• Optimize the design for lower gate count and lower power consumption
• Drive ISP design activities in close collaboration with the ISP algorithm team, ISP design leaders at other sites and the digital system design team
• Lead, supervise and mentor a team of RTL design engineers

Required profile

• MSEE, BSEE or equivalent degree
• 7+ years of digital design and verification-related experience
• 3+ years of project management and people management experience or skills
• Ability to lead teams and collaborate effectively with people in different functions
• Excellent time management, communication and interpersonal skills; result-oriented and adaptable to change

Required skills

• Knowledge of CMOS image sensors and image signal processing (ISP)
• System C/C++, SystemVerilog and Catapult HLS tool