Senior/Staff Engineer, Technical Manager (Design Verification)

About the role

A Senior/Staff Engineer, Technical Manager (Design Verification) is needed in Singapore, based at One North. The role covers developing and reviewing test plans, building verification environments and implementing coverage-driven verification for IC/ASIC designs.

Key responsibilities

• Develop and review test plans
• Develop verification environment and testbench at module, IP and SOC level
• Develop verification IP and reference models
• Implement tests using a randomization-based coverage-driven verification methodology
• Close functional and functional/code coverage
• Debug code with UVM, SystemVerilog, Verilog and SystemC, including low-power and formal verification

Required profile

• Bachelor's or Master's degree in EEE, Computer or IC design
• 4-10 years of verification experience
• IC/ASIC design verification on SOC, Ethernet, PCIe, DDR, USB and ARM CPUs
• Strong debugging ability
• Singaporeans and Singapore Permanent Residents are preferred

Required skills

• SystemVerilog/UVM and Verilog
• Synopsys, Cadence and Mentor simulator and debugging flow
• UNIX scripting with Python, Perl, makefile and cshell
• Low-power and formal verification (a plus)