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Senior/Staff Mid-End Engineer (STA/Synthesis)

bitdeer · Singapore

Senior 🇬🇧 English
Verilog SystemVerilog Synopsys Design Compiler Cadence Genus PrimeTime Innovus TCL Python Perl Shell UPF Clock Gating Power Gating Dynamic Voltage Scaling AXI NoC Mesh Torus Conformal FormalPro JasperGold

Job description

About the role

Bitdeer is seeking a Senior/Staff Mid-End Engineer specialized in static timing analysis and synthesis to drive ASIC design projects. The role focuses on logic synthesis, timing closure, and power optimization for high‑performance chips.

Key responsibilities

  • Perform logic synthesis and design optimization for ASIC designs.
  • Conduct static timing analysis (STA), constraint tuning, and clock‑tree synthesis (CTS) to close critical paths.
  • Resolve timing challenges across multi‑clock domains and high‑frequency data pipelines.
  • Implement low‑power techniques such as clock gating, power gating, and dynamic voltage scaling.
  • Optimize memory hierarchy to reduce energy consumption.
  • Collaborate with DFT engineers on scan chain insertion, MBIST for large SRAMs, and JTAG integration.
  • Debug synthesis, timing, and power issues before physical implementation.
  • Work closely with the physical design team on floorplanning, place & route, congestion analysis, and timing bottlenecks.
  • Provide constraints for high‑speed interconnects, NoCs, and large‑scale data movement.
  • Use formal verification and equivalence checking tools to ensure netlist correctness.

Required profile

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3–7 years of IC design experience with a focus on synthesis, timing closure, and power optimization.

Required skills

  • Proficiency in Verilog/SystemVerilog.
  • Experience with RTL‑to‑GDSII flow.
  • Synopsys Design Compiler, Cadence Genus, PrimeTime, and Innovus.
  • Strong understanding of static timing analysis, multi‑clock domain handling, and clock‑tree synthesis.
  • Familiarity with on‑chip interconnect architectures (AXI, NoC, mesh, torus).
  • Low‑power design methodologies (UPF, power gating, dynamic voltage scaling).
  • Scripting skills in TCL, Python, Perl, and Shell.
  • Formal verification tools such as Conformal, FormalPro, or JasperGold.

What we offer

  • A culture that values authenticity, diversity of thought, and inclusive collaboration.
  • An open workspace with a start‑up spirit within a fast‑growing global company.
  • Opportunities to work on cutting‑edge ASIC projects for Bitcoin mining and AI cloud solutions.

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Source : ats:breezy

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Published 1 week ago

Expires 1 month from now

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bitdeer

Singapore