Analog Layout Engineer

About the role

Marvell is seeking an Analog Layout Engineer to join its Central Engineering group. You will work with global teams to develop high‑performance analog and mixed‑signal IP that powers a wide range of products across automotive, storage, security, and networking.

Key responsibilities

• Run simulations and verifications using Cadence Virtuoso, iterating with designers to meet specifications.
• Collaborate with paired designers through regular meetings to share progress and resolve issues.
• Participate in the full development cycle, from floorplanning and layout to verification and delivery.
• Provide technical mentorship within the layout team and contribute to broader project discussions.
• Present status updates and technical solutions to global teams across multiple time zones.

Required profile

• Degree in Electrical Engineering (undergraduate or graduate) with a solid grasp of electrical concepts.
• Proven experience delivering high‑speed or precision analog circuits, preferably across multiple process nodes.
• Ability to take ownership of tasks ranging from individual cells to full‑chip interfaces.
• Strong communication skills for status reporting and cross‑team collaboration.

Required skills

• Cadence Virtuoso for analog layout and verification.
• Analog layout techniques, including floorplanning and microelectronic layer implementation.
• Design of high‑speed and precision analog circuits.
• Experience with multiple semiconductor process nodes.

What we offer

• Opportunity to work on cutting‑edge semiconductor IP used worldwide.
• Collaboration with diverse, global engineering teams.
• Professional growth within a fast‑moving, innovative environment.