Digital Design Verification Engineer (Staff/Sr. Staff)

About the role

As a Digital Design Verification Engineer you will join a high‑energy verification team that tackles ever‑more complex ASIC designs. You will help shape and execute state‑of‑the‑art verification strategies to ensure zero‑defect silicon.

Key responsibilities

• Develop and maintain UVM‑based verification environments.
• Perform C/C++ co‑simulation, system emulation, mixed‑mode and formal verification.
• Collaborate with design and architecture groups to define verification plans.
• Drive coverage analysis and debug complex verification failures.
• Contribute to continuous improvement of verification methodologies.

Required profile

• MSEE or BSEE in Electrical or Computer Engineering.
• 8 + years of relevant verification experience (open to outstanding fresh graduates).
• Disciplined, quality‑focused and driven for excellence.
• Strong team player with good communication skills.

Required skills

• UVM verification methodology.
• C/C++ programming.
• System emulation, mixed‑mode simulation and formal verification.
• Video processing and video analytics (a plus).
• General programming proficiency.

What we offer

• Competitive salary range SGD 7,000–14,000 per month.
• Full‑time permanent position at senior executive level.
• Opportunity to work on cutting‑edge video‑processing silicon on Jurong Island.