Package Pathfinding Architect, MTS

About the role

Micron's Package Pathfinding and Architecture organization works at the intersection of silicon, packaging, systems and customer needs, turning complex scaling challenges into technologies for next-generation platforms. This is a technical pathfinding role driving packaging technology for next-generation memory systems from datacenter to edge-AI, guiding long-term package technology direction and partnering with customers to turn innovative ideas into scalable products.

Key responsibilities

• Define next-generation package pathfinding and system architectures optimized for speed, performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
• Lead cross-stack co-optimization across silicon, package, board and system with a package-centric approach.
• Drive the long-term memory technology packaging strategy and influence industry standards.
• Work closely with silicon and system design teams and customers on disruptive solutions for edge-AI and datacenter memory products.
• Serve as a technical interface to internal partners, customers, business units and senior leaders.
• Develop AI-based EDA and internal automation toolsets to improve design cycle efficiency.
• Develop measurement automation for incoming substrate materials.

Required profile

• Master's degree or equivalent and industry experience in EE, CE, CS or a related field.
• At least 5 years of relevant experience in package design, electrical simulations and tools such as Ansys, Siemens and Cadence.
• Extensive hands-on experience in memory systems package design, signaling, IO design and PDN design.
• Deep understanding of memory timing, signaling, power and package process technology.
• Preferred: PhD in a related technical field, recognized technical leadership across multiple products, and experience in signal and power integrity, mechanical and reliability, and thermal analysis.

Required skills

• Working knowledge of EDA tools for electronic packaging design, analysis and simulation, including Cadence, Siemens and Ansys.
• Strong understanding of memory timing and analysis, and familiarity with memory package and die-level specifications.
• Familiarity with signal and power integrity concepts and tools.
• Proficiency in data analysis tools such as JMP, Python or MATLAB.
• Experience applying AI or LLMs for engineering efficiency.
• Analytical, problem-solving and data-driven mindset, effective cross-functional communication, and attention to detail.