Physical Design Intern (Master's Degree)

About the role

Marvell's central physical design team develops the physical implementation of AI infrastructure and ASIC chips, turning RTL designs into manufacturing-ready GDS. The internship takes part in physical design implementation and verification of complex SOC designs, covering the RTL-to-GDS flow including floorplanning, placement, clock tree synthesis, routing, timing closure and physical verification.

Key responsibilities

• Block-level layout implementation and timing closure
• Static timing and crosstalk analysis and timing closure
• Synthesis and physical synthesis
• Power, IR and EM analysis
• Physical verification (LVS, DRC, ERC, ANT)
• ECO implementation

Required profile

• Currently pursuing a Master's degree in Electronic Engineering, Microelectronics or a related discipline
• Basic understanding of semiconductor devices and electronic circuits
• Detail-oriented, self-motivated team worker with good verbal and written communication skills
• Previous experience in physical design and automatic place-and-route, and in synthesis/STA, is a plus

Required skills

• Scripting/programming with Tcl/Tk, Perl or Python
• Knowledge of Synopsys or Cadence place-and-route tools is a plus

The position may require access to technology or software subject to U.S. export control laws, so applicants must be eligible to access export-controlled information. Candidates are not allowed to use AI tools during interviews.