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Principal Engineer - Hardware Sustaining

hpe · Singapore

New
Senior 🇬🇧 English
Verilog RTL FPGA CPLD SerDes DDR PCIe Signal Integrity Power Integrity PLM Schematic Capture Layout

Job description

About the role

Hewlett Packard Enterprise's Hardware Sustaining organization within the Networking Products and Technologies (NPAT) group drives product hardware quality to ensure a best-in-class customer experience. This Principal Engineer role leads hardware failure analysis on HPE networking products and is designed as onsite, with the expectation of working primarily from an HPE office.

Key responsibilities

  • Lead failure analysis of complex hardware problems, covering CPU, networking ASICs, power, clocking, high-speed signals, optics and more.
  • Drive corrective and preventive actions: immediate containment or work-arounds, validation of the final fix, identification of other systems affected, and sharing of lessons learned.
  • Provide technical leadership in hardware quality and reliability, guide and mentor junior team members, and collaborate with engineering, manufacturing, ODM and supply chain teams.
  • Document findings and lessons learned, and give regular failure analysis updates and final RCCA reports to internal stakeholders and customer support.

Required profile

  • Bachelor's or Master's degree in electrical engineering (12+ years of experience, or 10+ years with a Master's).
  • Proven track record of root cause and corrective action on complex hardware, preferably in networking.
  • Demonstrated experience as a technical leader or subject matter expert, with strong leadership and mentoring skills.
  • Excellent written and verbal communication in English and the local language.

Required skills

  • Hardware design processes and tools: schematic capture, layout, BoM, PLM tools.
  • Debugging of networking hardware, including 20-layer boards with 50G+ signals, and signal and power integrity.
  • High-speed (PCIe, SerDes, DDR) and low-speed (I2C, SPI) interface design and debug.
  • FPGA and CPLD design and debug, Verilog RTL.
  • Scripting for hardware design, test and debug.

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Source : ats:workday

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Published 22 hours ago

Expires 1 month from now

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hpe

Singapore