Principal Memory Architect (3D-NAND)

About the role

Brightecs Innovation Pte. Ltd. (BIP), a Singapore-based startup focused on silicon IP for intelligent computing, is looking for a Principal Memory Architect. The role defines the overall 3D-NAND memory architecture and works closely with device and process teams to deliver high-performance NAND products.

Key responsibilities

• Define the overall 3D-NAND architecture, including array organization (plane/bank/page/block), word line/bit line layout and shared resource strategies.
• Lead feasibility studies, technical risk assessments and roadmap planning, promoting IP reuse, scalability and future technology node evolution.
• Design and optimize program/erase/read algorithms, balancing speed, endurance, data retention and interference management.
• Develop ECC strategies and evaluate BCH, LDPC (hardware or software decoding) and other solutions against area, latency, power and error correction capability.
• Define page and block management logic, supporting copy-back, multi-plane operation, suspend/resume and background erase.
• Balance performance, die size, active and standby power and reliability (P/E cycles, data retention) to fit consumer, enterprise or automotive product positioning.
• Work with device and process teams on circuit and algorithm optimization for 3D stacked structures (CT/FG charge trapping, vertical channels, word line stacking).
• Help select and customize ONFI/Toggle Mode interfaces, including register mappings, command extensions and low-power modes.
• Coordinate cross-team technical reviews, define architecture specifications and simulation verification standards, and support post-silicon verification, yield analysis and customer issue resolution.

Required profile

• Master's degree or above (PhD preferred) in microelectronics, electrical or computer engineering or a related field.
• 8+ years of flash memory development experience, including at least 5 years as an architecture or key technology lead.
• Deep knowledge of 3D-NAND physical structure and operation, including charge trapping or floating gate technologies, vertical channels, crosstalk and multi-bit memory (TLC/QLC/PLC).
• Familiarity with ONFI 4.x and Toggle 3.0 interfaces.
• Excellent systems thinking, ability to coordinate circuit, device, firmware, verification, testing and product teams, and strong technical writing and decision-making communication.
• Ability to follow cutting-edge trends such as HBM-NAND hybrid storage and in-memory computing, and to drive architectural innovation and patents.
• Experience delivering complete NAND architectures and mass-producing 64-layer or higher 3D-NAND is a plus; publication of NAND papers at ISSCC, VLSI or IMW is a plus.

Required skills

• 3D-NAND architecture and operation
• ECC (BCH/LDPC) and NAND controller collaboration
• ONFI 4.x and Toggle 3.0 interfaces
• Reliability modeling awareness (TDDB, HCI, RTN)