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Principal Physical Design Engineer

Astera Labs · Singapour

New
Senior 🇬🇧 English
ICC2 Innovus Calibre Voltus RedHawk Tcl Python Perl CTS DRC LVS ERC

Job description

About the role

Astera Labs, which builds rack-scale AI connectivity solutions, is looking for a Senior Physical Design Engineer to join its high-performance design team. The team works on next-generation transceiver intellectual property (IP) targeting TSMC 3nm and other advanced technology nodes.

Key responsibilities

  • Perform block-level and top-level physical implementation, including floorplanning, placement, clock tree synthesis (CTS), routing and physical verification for high-speed designs.
  • Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area and power convergence.
  • Apply physical design techniques for multiple voltage and frequency domains, hierarchical design and physical-aware synthesis.
  • Work on EM/IR analysis and power grid optimization, congestion analysis and mitigation, clock skew optimization and RC extraction-aware placement and routing.
  • Integrate IPs and top-level blocks, supporting floorplan development and chip partitioning for high-speed transceivers.
  • Perform ECO implementation and help with tapeout signoff, keeping DRC, LVS, ANT, CELL and ERC databases clean.
  • Use industry-standard tools such as ICC2, Innovus, Voltus, RedHawk and Calibre.
  • Develop automation scripts in Tcl, Python or Perl to improve physical design flows.

Required profile

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or a related field.
  • 5-10 years of experience in physical design, preferably with advanced technology nodes.
  • Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
  • Experience on high-frequency datapath and DSP-related designs.
  • Solid scripting skills and good problem-solving skills; able to work in cross-functional teams.

Required skills

  • Floorplanning, placement, CTS, routing and IR drop mitigation
  • DRC, LVS, ANT and ERC signoff checks and debugging
  • Hands-on use of Synopsys ICC2, Cadence Innovus, Calibre and Voltus
  • Tcl, Python or Perl scripting

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Published 3 hours ago

Expires 1 month from now

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Astera Labs

Singapour