QEM Engineer - Wafer Level Reliability (Fab 10N/X)

About the role

Micron is hiring an Engineer for its QEM Product Quality Engineering team at Fab 10N/X, focused on wafer-level reliability. The role takes reliability accountability for Singapore Fab 10, working on cross-functional projects and tasks that cover semiconductor reliability, process technology and quality monitoring.

Key responsibilities

• Understand semiconductor reliability failure mechanisms and physics, and RG and FG process technology and risks to manufacturing quality
• Understand probe testing, device datasheet specifications and device characterization
• Own Fab reliability performance, define the Wafer Level Reliability (WLR) sampling plan, the Outgoing Quality and Reliability Monitoring (OQRM) matrix, and lead Fab process SWR studies and conversion risk assessments
• Partner with Fab 10 PI/PEE and Global TD, QE, Product and Test engineering teams to meet intrinsic targets through process improvement
• Assess risk for Class 1 and Class 2 process conversions and advise on data collection and conversion roadmaps
• Develop WLR capability as a proxy for equivalent package-level reliability tests, and deepen understanding of Product Intrinsic Scorecards (endurance, retention, program disturbance, X-temp, etc.)
• Act as subject matter expert on reliability fail modes, their detection and drivers, and contribute to quality projects for excursion mitigation
• Provide corrective and preventive actions for CQE and FEMQA teams on customer feedback regarding quality and product issues

Required profile

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Microelectronics, Materials Science, Physics, or Data Science and Analytics (equivalent preferred)
• NAND reliability experience or EFA experience is an added advantage
• Excellent problem-solving and analytical skills
• Highly motivated, growth-minded individual who integrates AI-assisted tools into daily work responsibly

Required skills

• Good understanding of CMOS device physics (added advantage)
• Knowledge of NAND device operation and datasheets (added advantage)
• Understanding of reliability testing flow, probe test methodology and device characterization, including array operation and customer features and specifications (added advantage)