RTL Design Engineer (Memory & Interconnect)

About the role

Campus Singapore is hiring an RTL Design Engineer focused on memory subsystems and data movement, working on AI chips. The role combines microarchitecture design, RTL implementation and performance analysis, with AI tools integrated into the design flow.

Key responsibilities

• Use AI tools across the digital IC front-end flow and integrate automated agents into design flows, optimising them continuously.
• Drive microarchitecture design, iteration and RTL implementation for memory subsystems and data movement.
• Perform functional evaluation and performance analysis, and support pre-simulation verification.

Required profile

• Master's degree or above in Electronics, Computer Science or a related field.
• No prior experience required; digital IC project experience is a plus.
• Learning ability, logical thinking and technical potential are valued more than experience.
• Good communication, teamwork and fluent English.

Required skills

• Basic Verilog/SystemVerilog and digital circuit fundamentals.
• Preferred: knowledge of memory controllers (DDRC, HBM_Ctrl, 3DDRAM), interconnect (NoC) or AI chips.

What we offer

• 1:1 mentorship from senior experts.
• Unrestricted access to world-leading AI tools.
• Work on world-class AI chips.
• Join core projects from day one: full front-end flow with AI agents, block-level microarchitecture/RTL, and C model build and test for architecture exploration.