Senior ASIC Design Engineer

About the role

We are seeking a Senior ASIC Design Engineer to join our growing team in Singapore, focusing on AI compute subsystems. The role involves leading micro‑architecture and RTL development while ensuring performance, power and area targets are met.

Key responsibilities

• Develop micro‑architecture and RTL for AI compute subsystems.
• Analyze performance, power and area (PPA) to meet strict cost and energy budgets.
• Contribute to RTL design of SoC modules and assist in IP core integration.
• Support chip‑level system design, including clock/reset architecture, low‑power techniques and bus architecture.
• Collaborate with verification and testing teams for module‑level and system‑level validation.
• Assist front‑end engineers with netlist delivery and timing issue resolution.

Required profile

• Bachelor’s degree or higher in Electrical Engineering or equivalent.
• 3+ years of experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals and CPU/cache architectures.
• Familiarity with ASIC design flow and EDA tools such as Synopsys and Cadence.

Required skills

• Proficiency in Verilog HDL.
• Experience with synthesis, timing analysis and low‑power design methodologies.
• Knowledge of standard bus protocols (e.g., AMBA, AXI, AHB, APB) and DMA.