Senior Software Engineer - Ultra Low Latency Risk Engine Lead Developer

About the role

Citi Equities Technology is looking for a Senior Software Engineer to lead the development of its next-generation ultra low-latency Risk Engine for cash equities within the Equities Electronic Execution (Electronic Trading) team. The role owns latency-sensitive risk-checking components in the trading hot path, with hands-on technical work alongside leadership duties such as mentoring engineers, driving architecture decisions and coordinating delivery across global development centers.

Key responsibilities

• Design, develop and maintain the ultra low-latency, in-line Risk Engine for real-time pre-trade risk checks, position limits and exposure controls across cash equities electronic execution flows.
• Architect and optimize high-performance, lock-minimal, multi-threaded components that make risk decisions in the sub-microsecond to low-microsecond range.
• Integrate risk and position components with Client Connectivity, Market Access layers and high-throughput market data feed handlers.
• Tune JVM performance, avoid garbage collection pauses, and apply native (C++/Rust) performance engineering to remove latency jitter.
• Perform system-level tuning to minimize end-to-end latency and jitter across the risk and execution path.
• Mentor engineers, drive architecture decisions and coordinate delivery across APAC, EMEA and NAM.

Required profile

• 10+ years of software engineering experience, with hands-on experience building risk management, position-keeping or other latency-critical systems for cash equities electronic trading or algorithmic trading at a global investment bank or equivalent.
• Bachelor's degree in Computer Science, Engineering or a related field, or equivalent professional experience.
• Background in real-time distributed risk management systems for cash equities flow products, including asynchronous, event-driven architectures.
• Excellent communication skills and ability to work with globally distributed stakeholders.
• Working knowledge of regional exchange microstructure and the regulatory regimes governing cash equities electronic trading and risk controls.

Required skills

• Low-latency Java and/or C++ (Rust a plus), including multi-threading, concurrency, lock-free data structures, Java NIO and JVM/GC tuning.
• Low-latency messaging and IPC frameworks such as Aeron or Solace.
• NUMA-aware design, CPU core pinning/affinity, Linux kernel/OS tuning and low-latency networking (kernel bypass, RDMA).
• Automated testing, test-driven development and quality engineering for mission-critical systems.