Senior/Staff ISP RTL Design Engineer

About the role

The ISP RTL Design Engineer will translate image‑signal‑processing algorithms into efficient hardware implementations. Working closely with the ISP algorithm team, you will define architecture, verify functionality and optimise for gate count and power.

Key responsibilities

• Implement ISP algorithms in hardware using Verilog, SystemVerilog and/or SystemC (High‑Level Synthesis).
• Define ISP hardware architecture based on product features, performance targets, gate‑count and power estimates.
• Verify logic at both ISP and digital system levels.
• Drive optimisation to reduce gate count and minimise power consumption.
• Collaborate closely with the ISP algorithm team throughout the design cycle.

Required profile

• Minimum MSEE or BSEE (or equivalent) with at least 3 years of digital design and verification experience.
• Experience with CMOS image sensors and image‑signal‑processing pipelines.
• Strong debugging and problem‑solving abilities.
• Good communication and interpersonal skills.

Required skills

• Verilog
• SystemVerilog
• SystemC
• C++
• High‑Level Synthesis (HLS)
• Catapult HLS tool
• CMOS Image Sensor knowledge
• Image Signal Processing (ISP) expertise