Staff Digital IC Design Engineer

About the role

We are looking for a seasoned Staff Digital IC Design Engineer to lead RTL-level digital design and verification activities. You will work closely with the backend team to ensure successful synthesis, place‑and‑route, and test implementation for mixed‑signal IC projects.

Key responsibilities

• Develop RTL code, perform problem solving and functional verification.
• Support digital functional verification and FPGA validation.
• Collaborate with backend engineers on digital synthesis, place‑and‑route, Design‑for‑Test and static timing analysis.
• Lead and mentor junior engineers, reviewing their work and providing guidance.
• Define and implement custom digital interfaces (I2C, 3‑wire, single‑wire) and finite‑state machines.

Required profile

• Bachelor or Master in Electronics/Electrical Engineering with mixed‑signal IC design or verification experience.
• 7‑10 years of industry experience in application/validation.
• Strong proficiency in Verilog coding, simulation and verification.
• Experience designing RTL for synchronous and asynchronous systems with multiple clock domains.
• Basic knowledge of logic synthesis, place‑and‑route, static timing analysis and logic equivalence checking.

Required skills

• Verilog
• RTL design and FPGA verification
• Cadence tools: Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus, Virtuoso
• Custom digital interfaces (I2C, 3‑wire, single‑wire)
• Finite‑state machine and register‑map development
• Mixed‑signal IC design, DFT, static timing analysis
• Logic synthesis, place‑and‑route, multiple clock domains

What we offer

• Competitive monthly salary range SGD 7,000‑9,000
• Full‑time permanent position
• Opportunity to lead a high‑impact engineering team