Staff Layout Engineer

About the role

The Library Group within Central Engineering focuses on circuit design for memory, I/O and standard cells. We are looking for an experienced Staff Layout Engineer to lead IC layout activities, ensure high‑quality designs and mentor junior engineers.

Key responsibilities

• Interpret and apply layout guidelines, new process rules and technical requirements for standard cells, I/O and memories.
• Plan layout floor‑planning, schedule timelines and deliver complete, verified layouts on schedule.
• Perform physical verification (LVS, DRC, ERC, antenna, electromigration) using CALIBRE and Hercules tools.
• Lead technology reviews, document methodology, flow and guidelines, and train junior staff.

Required profile

• Minimum 8 years of IC layout experience in sub‑micron processes (16nm, 7nm, 5nm, 2nm, A14 and below).
• Strong background in memory layout design and physical verification.
• Self‑reliant, able to work independently and collaboratively within a team.

Required skills

• Cadence layout and schematic capture.
• CALIBRE and Hercules verification tools.
• Cadence Virtuoso (XL, VXL or EXL).
• Floor‑planning, hierarchy layout and chip integration.
• Script and SKILL programming (plus).