Staff Layout Engineer (Memory)

About the role

Broadcom's Library Group, part of the Central Engineering Group, focuses on circuit design for memory, I/O and standard cells. It is looking for a Staff Layout Engineer who can deliver high-quality IC layouts for memory, I/O and standard cells, including new process rules and floor planning.

Key responsibilities

• Understand and apply layout guidelines, standard cell and I/O memory rules, and new process rules for quality layouts.
• Schedule timelines and handle layout floor planning.
• Complete quality layout and verification within the planned schedule, without supervision for an experienced engineer.
• Learn quickly new methodologies, share ideas and communicate well with the library team.
• Lead or train a team of junior engineers and lead new technology reviews to document layout methodology, flow and guidelines.

Required profile

• Minimum 8 years of IC layout experience.
• Strong layout knowledge in submicron processes such as 16nm, 7nm, 5nm, 2nm, A14 and below.
• Experience in digital layout (standard cell, memory, I/O); analog layout experience is a plus.
• Able to work independently and in a team, with good leadership qualities in project management.
• Must be available to relocate to Singapore immediately.

Required skills

• Cadence layout tools (Virtuoso XL, VXL or EXL) and CALIBRE verification.
• Memory layout design and physical verification: LVS, DRC, ERC, antenna and electromigration.
• Floor planning, hierarchy layout and chip integration; memory compiler experience is a plus.
• Script programming and SKILL programming are a plus.