Associate Staff / Staff Implementation Design Engineer

About the role

Silicon Labs is seeking an Associate Staff Design Engineer to join its Silicon Engineering team. The role leads and takes part in the backend implementation flow, including synthesis, static timing analysis (STA), logic equivalence and low-power checks, and timing sign-off of high-performance SoCs and ASICs. It is based near Tai Seng MRT station and is listed as hybrid.

Key responsibilities

• Develop, manage and validate timing constraints for the RTL-to-GDSII flow with Design and DFT teams
• Execute STA on digital blocks and top-level designs, and help generate CTS specs with Design and PnR engineers
• Run logical equivalence checks, develop low-power and UPF checks, and generate and interpret timing reports
• Implement timing ECOs, check CDC, false paths and multicycle paths, and contribute to timing methodology and automation
• Lead the end-to-end physical design flow for complex SoCs and IP blocks, and own PPA metrics
• Mentor junior engineers and drive EDA tool flow automation

Required profile

• Bachelor's or Master's degree in ECE, EEE, VLSI or a related field
• 9-10 years of experience in ASIC physical design
• Must have exposure to the full BE cycle, including synthesis, place & route, logic equivalence, UPF and low-power checks, STA and PV sign-off
• Preferred: chip-level integration, DFT, floor planning, PnR, multi-site collaboration, and Perl/Tcl/Python automation

Required skills

• Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime)
• Low-power techniques (UPF/CPF, power gating, DVFS)
• Architecture-to-GDSII flows and sign-off requirements

What we offer

• Medical and dental insurance covering spouse and children
• Bi-yearly health screening and flu vaccination
• Hybrid work arrangement