Design Verification Engineer II

About the role

Silicon Labs' IoT Digital Design team builds Wireless MCU SoCs, which include an embedded CPU system with analog and digital peripherals, advanced security and power management, and custom RISC-V cores and AI/ML components. This Design Verification Engineer II role sits within that team, responsible for verifying SoC and IP blocks and mixed-signal designs.

Key responsibilities

• Develop and execute verification plans for SoC/IP blocks and mixed-signal designs.
• Build and maintain SystemVerilog/UVM-based testbenches.
• Create directed and constrained-random test cases.
• Drive functional coverage closure, assertions and regression analysis.
• Debug RTL and verification failures across simulation and emulation environments.
• Collaborate with RTL designers, architecture teams, firmware/software teams and validation engineers.
• Improve verification methodologies, automation and CI flows.
• Support pre-silicon and occasionally post-silicon debug activities.
• Mentor junior engineers and contribute to verification strategy.

Required profile

• BS/MS in Electrical or Computer Engineering.
• 5-10+ years of verification experience.
• Experience with wireless SoCs, MCU subsystems, AMBA/AXI/APB protocols, embedded systems and low-power IoT silicon.

Required skills

• SystemVerilog and UVM/OVM
• RTL and GLS simulation and debug
• Functional coverage and assertions (SVA)
• Python, Perl and TCL scripting
• SoC/IP verification and low-power verification concepts
• CDC/RDC verification and mixed-signal / AMS verification

What we offer

• A tight-knit team with a strong work-life balance.
• Medical and dental insurance covering spouse and children.
• Bi-yearly health screening and flu vaccination.
• Hybrid work arrangement.