Director, Package Quality and Reliability

About the role

The Director, Package Quality & Reliability Engineering leads the execution and continuous improvement of package reliability, qualification and failure analysis across new product introductions (NPI) and high-volume manufacturing (HVM). The role ensures robust package quality and reliability, identifies and mitigates key risks and enables successful product ramps across mobile, automotive, data center and AI/HPC applications. It works closely with Package Development Engineering, front-end fabrication, manufacturing and quality teams.

Key responsibilities

• Lead package reliability qualification for NPI and ongoing reliability monitoring in HVM
• Resolve reliability risks such as chip-to-package interaction, interconnect reliability, thermo-mechanical stress and material-related failures
• Improve reliability test coverage and methodologies, and ensure robust qualification processes and test plans
• Integrate Design for Reliability (DFR) and Design for Manufacturability (DFM) with PDE, and work with front-end fab teams on silicon-packaging interfaces
• Support customer engagements and provide technical input on risk assessments, process and material changes, and manufacturing excursions
• Lead or support failure analysis and root cause investigations (e.g. 8D) for quality issues, qualification failures and field returns
• Build and lead a team of engineers, set KPIs and operating rhythms, and manage budgets and resource planning
• Support continuous improvement, reliability data analytics, supplier interactions and escalation of critical issues

Required profile

• Bachelor's degree in Materials Science, Mechanical, Electrical or Chemical Engineering (Master's or Ph.D. preferred)
• 12+ years in semiconductor packaging, reliability or manufacturing
• 5+ years in people management or technical leadership
• Experience in high-volume manufacturing with package quality and reliability exposure

Required skills

• Package reliability test methods (temperature cycling, HAST, MSL/preconditioning) and JEDEC, AEC-Q standards
• Failure analysis techniques (cross-sectioning, SAM, X-ray, SEM/EDX) and root cause analysis
• Chip-to-package interaction, thermo-mechanical stress and reliability failure mechanisms
• Strong leadership, collaboration, structured problem-solving and communication skills
• Preferred: digital fluency with AI-enabled tools, memory products (DRAM, NAND, HBM), advanced packaging, automotive/AI/HPC reliability, predictive analytics, OSAT and supplier experience