E5 MTS SMTS NAND Design Rule Engineer - Process Integration

About the role

Micron is hiring an E5/MTS/SMTS NAND Design Rule / Process Integration engineer to support the development and high-volume manufacturing of advanced 3D NAND technologies. The role drives design-rule and PDK deliverables, partners across process integration and design organizations, and ensures quality, documentation and timely execution across R&D and production programs.

Key responsibilities

• Lead the release of design rules and PDK deliverables, and manage DRC waivers, mask definitions and mask reviews for R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Partner with stakeholders across Array and CMOS Process Integration, Devices, Layout and Design, Modeling, Scribe and Frame, unit process areas (e.g. PHOTO/OPC/CMP) and Quality and Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Work with Yield Enhancement, Product Engineering, Defect Analysis and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules and maintain proactive communication with stakeholders, escalating issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.

Required profile

• PhD in Electrical Engineering, Microelectronics, Physics or Semiconductor Materials Science with 5+ years of relevant experience; or Master's degree with 8+ years; or bachelor's degree with 13+ years in the semiconductor industry (Process Integration, Yield Enhancement, Product Engineering, Test Structure Development or Unit Process Development).
• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge.
• Understanding of 3D NAND process flow and major NAND components (bit-line sensing, word-line driver, data path, analog circuits).
• Familiarity with CAD group interactions, data post-processing and data transfer from design databases to reticles.
• Preferred: prior experience in R&D for NAND or other memory technologies.

Required skills

• Hands-on exposure to PDK, design rules and layout (including minor layout work).
• Proficiency with CAD tools such as Cadence Virtuoso, K2View and Mentor Graphics DRC/RVE (or equivalent) is a must.
• Demonstrated ability to resolve complex issues and communicate clearly under pressure.