I/O Design Engineer

About the role

Broadcom’s Central Engineering Group is looking for an experienced I/O Design Engineer to contribute to analog and mixed‑signal IC projects, including cutting‑edge AI programs on advanced process nodes. You will work with a collaborative team of engineers on a variety of IP and I/O designs.

Key responsibilities

• Design CMOS I/O blocks, high‑precision bandgap references, op‑amps, comparators and power‑on‑reset circuits.
• Run AC/DC, signal‑integrity, jitter and power simulations to validate performance.
• Perform transistor reliability and EMIR analysis.
• Collaborate with layout teams to oversee physical design and verification.
• Develop Verilog, Synopsys Liberty and IBIS models.
• Create and maintain technical documentation such as datasheets, application notes and integration guides.
• Support chip‑level integration and silicon bring‑up in test chips and customer products.

Required profile

• MS or PhD in Electrical Engineering.
• 6+ years of experience in I/O or analog circuit design.
• Deep proficiency with Cadence Virtuoso and SPICE/Spectre simulation tools.
• Strong knowledge of I/O protocols (GPIO, I2C, I3C, eMMC, RGMII, SPMI).
• Familiarity with ESD, EMI and signal‑integrity considerations.
• Experience with advanced CMOS FinFET and GAA process nodes.

Required skills

• Cadence Virtuoso
• SPICE/Spectre
• Verilog
• Synopsys Liberty
• IBIS modeling
• GPIO, I2C, I3C, eMMC, RGMII, SPMI protocols
• ESD and EMI mitigation
• Signal integrity analysis
• CMOS FinFET and GAA node technologies
• Analog and mixed‑signal IC design