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NAND Design Rule Manager

micron · Fab 10N/X

New
Senior 🇬🇧 English
Cadence Virtuoso K2View Mentor Graphics DRC/RVE PDK

Job description

About the role

Micron is looking for a NAND Design Rule Manager to lead a team supporting both development and large-scale production of advanced 3D NAND technologies. The role ensures accurate design-rule and PDK results, high quality and strict documentation across R&D and production.

Key responsibilities

  • Lead the release of design rules and PDK deliverables, and coordinate DRC waivers, mask definitions and mask reviews for R&D and production.
  • Own program execution from kickoff through end-of-life.
  • Partner with Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit processes (PHOTO/OPC/CMP) and Quality & Reliability on new 3D NAND generations.
  • Ensure high-quality Build Rule Checks (DRCs) and timely disposition of deviations and exceptions.
  • Work with Yield Improvement, Product Engineering, Defect Analysis and Quality Assurance to identify layout- or database-related issues and prioritize fixes.
  • Build and evaluate test structures to generate data for next-generation devices and assess process margin on current technologies.
  • Communicate status, risks and resolutions clearly across functions and management levels.
  • Define and track sub-milestones within PDK/DBR/TO schedules and drive continuous improvement, including AI-enabled enhancements.

Required profile

  • PhD in Electrical Engineering, Microelectronics, Physics or Semiconductor Materials Science with 5+ years of relevant experience; or Master's with 8+ years; or Bachelor's with 13+ years in the semiconductor industry.
  • Direct experience with PDK, design rules and layout, including small layout assignments.
  • Solid understanding of semiconductor device physics and VLSI silicon processing and integration flow.
  • Understanding of 3D NAND process flow and major NAND components (bit-line sensing, word-line driver, data path, analog circuits).
  • Preferred: prior leadership experience in R&D for NAND or other memory technologies.

Required skills

  • CAD software such as Cadence Virtuoso, K2View and Mentor Graphics DRC/RVE or equivalents.
  • Ability to resolve complex issues and communicate clearly under pressure.

Questions fréquentes

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Source : ats:workday

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Published 1 day ago

Expires 1 month from now

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micron

Fab 10N/X