NAND PI Design Rule Sr. Engineer

About the role

Micron is hiring a NAND PI Design Rule Senior Engineer at Fab 10N/X. The role covers design rule releases, DRC waivers and mask reviews for R&D and production designs, and drives key milestones from project kick-off through end-of-life. It works closely with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability teams.

Key responsibilities

• Own design rule releases, DRC check waivers, mask and related DRC definitions, mask review and sign-off, and process requirement specifications for R&D and production designs.
• Drive or contribute to project milestones from kick-off to end-of-life, and define sub-milestones within the layout schedule.
• Collaborate with stakeholders to direct development of a new advanced NAND generation and ensure clear communication between NAND Design Rule and other teams.
• Ensure released DRCs react appropriately to deviations from design rules and are properly documented.
• Work with Yield Enhancement, Product Engineers, defect analysis and Quality Assurance teams on process issues related to database layout, prioritising solutions with Process Integration and Advanced Mask Design.
• Help design and evaluate test structures to provide data for next-generation devices and to quantify process margin on current devices.
• Identify and resolve process issues and process-window versus die-size conflicts caused by database layout or layout techniques.
• Document and feed back R&D design-rule improvements to production parts still in design, and support multi-functional issue resolution.

Required profile

• Master's degree with at least 5 years of experience, or Bachelor's degree with at least 8 years of experience in the semiconductor industry.
• Experience in Process Integration, Yield Enhancement, Product Engineering, Test Structure Development or Unit Process Development.
• Understanding of the advanced NAND process flow and major NAND components such as BL sensing, word-line driver and CMOS under array.
• Familiarity with CAD group interactions, data post-processing and transferring data from the database to the reticle.

Required skills

• Exposure to design and layout, with ability to do minor layout.
• Experience with CAD tools such as Cadence Virtuoso, K2view and Mentor Graphics DRV/RVE is highly desired.