Research Fellow – Semiconductor Advanced Packaging

About the role

The School of Electrical and Electronic Engineering at Nanyang Technological University seeks a Research Fellow to develop low‑temperature Cu/dielectric hybrid bonding for fine‑pitch, high‑density interconnects. The role combines materials selection, wafer‑level process development, and reliability testing to create a manufacturable 3D‑integration solution.

Key responsibilities

• Develop and execute a Cu–Cu hybrid bonding flow for fine‑pitch 3D integration.
• Optimize process windows (pressure, temperature, anneal, surface activation) to reduce contact resistance and voids.
• Characterize materials and interfaces using optical profilometry, SEM/TEM, surface chemistry, and electrical IV measurements.
• Validate reliability and scalability through thermal cycling, high‑temperature storage, and electrical stress tests on prototype stacks.
• Produce technical reports, presentations, and maintain rigorous documentation, version control, and safety compliance.

Required profile

• PhD in Materials, Microelectronics, Electrical & Electronic Engineering, or a related field.
• Hands‑on experience in semiconductor cleanroom processes (Cu interconnect, lithography, etching, CMP, plasma, anneal).
• Proven ability to perform detailed material and interface characterization.
• Strong analytical mindset for reliability testing and failure analysis.

Required skills

• Semiconductor process development (Cu interconnect, hybrid bonding)
• Lithography, etching, CMP, plasma, anneal techniques
• Optical profilometry, SEM, TEM, XPS, AFM, electrical probing
• Design of Experiments (DoE) and statistical analysis (Python, Matlab a plus)
• Process integration, optimization, root‑cause analysis