Semiconductor R&D Engineer – Thermal Compression Bonding

About the role

The Semiconductor R&D Engineer will lead the development, evaluation and optimisation of advanced Thermal Compression (TC) bonding and chip‑attach processes for next‑generation packaging technologies such as chiplet integration, HBM and 2.5D/3D architectures. You will establish robust bonding recipes, ensure precise co‑planarity and alignment, and drive TC bonder tools from concept validation to internal and customer qualification.

Key responsibilities

• Develop TC bonding processes for CoWoS PKG product family and CPO.
• Design, qualify and improve bonding tools and hardware.
• Control warpage and co‑planarity across the production line.
• Conduct failure analysis and enhance reliability of bonded assemblies.
• Lead customer development programmes and technology transfer activities.
• Manage assigned projects and drive yield improvement initiatives.
• Perform yield failure analysis and implement corrective actions.

Required profile

• Bachelor’s degree or higher in Engineering, Material Science, Chemistry, Chemical Engineering, Electronics or related fields.
• Minimum three years of R&D or mass‑production experience in Thermal Compression Bonding, flip‑chip assembly or micro‑bump bonding.
• Proven track record of managing customer development programmes and meeting technical requirements.
• Strong understanding of advanced semiconductor packaging, thermal‑mechanical bonding behaviour and warpage control.
• Excellent experimental design (DoE) and failure analysis capabilities.
• Ability to prepare technical documents and deliver presentations to internal and external stakeholders.

Required skills

• Thermal Compression Bonding
• Flip‑chip assembly
• Micro‑bump bonding
• Design of Experiments (DoE)
• Failure Analysis
• Technical data reporting
• Technical documentation

What we offer

• Competitive remuneration package (SGD 4,000‑6,500 per month).
• Comprehensive range of employee benefits.