Senior Engineer – Bump Mask Design

About the role

We are seeking a Senior Engineer to lead bump mask design activities, ensuring designs meet customer requirements and align with UTAC’s guidelines, design rules, and process capabilities.

Key responsibilities

• Perform bump mask design to satisfy customer specifications while adhering to UTAC’s design guidelines and process capabilities.
• Optimize layouts for electrical performance, manufacturability, yield, reliability, and cost.
• Prepare complete design outputs in required tooling formats and secure approvals from authorized personnel and customers.
• Maintain documentation, revision control, and traceability in line with design verification procedures.
• Develop and update bump mask design rules and DFMEA, supporting new technologies and process improvements.
• Collaborate with Process, Assembly, Product Engineering, and suppliers to continuously improve design guidelines.

Required profile

• Bachelor’s degree in Engineering, Science, or related technical discipline.
• Minimum 3 years of bump mask design experience with solid understanding of semiconductor bumping processes.
• Strong analytical and problem‑solving abilities with high attention to detail.
• Effective communication and teamwork skills.

Required skills

• Proficiency in AutoCAD (minimum 3 years hands‑on experience).
• Experience with Cadence APD, Allegro, or other PCB/package substrate layout design tools (advantageous).
• Knowledge of semiconductor IC packaging and assembly processes.
• Familiarity with design verification, documentation, and revision control processes.