Senior Engineer – Integration & Yield (Semiconductor)

About the role

We are seeking a Senior Engineer to lead integration and yield activities within our semiconductor fab. The role focuses on defect excursion control, driving defect reduction, and improving overall yield.

Key responsibilities

• Supervise YE Associate Engineers and wafer tech operators across 24/7 inline shifts.
• Train and certify engineers on recipe creation and defect source knowledge.
• Maintain and enhance SOP/OCAP, and support internal/external audits.
• Perform inline failure analysis using FIB, SEM, EDX, and optical microscopy.
• Develop and run recipes on Brightfield, Darkfield and other defect inspection tools.
• Conduct partition analysis, build defect source libraries, and generate detailed reports.
• Track inline defect performance by layer, process, tool, and chamber on a weekly basis.
• Execute killer‑ratio analysis and defect characterization across process tools.
• Lead continuous improvement initiatives with modules, vendors, and equipment teams.
• Liaise with process engineers to troubleshoot defects and support low‑yield investigations.
• Automate daily activities to accelerate troubleshooting.
• Authority to stop shipment or production to ensure wafer quality compliance.

Required profile

• Master’s or Bachelor’s degree in Electrical/Electronic Engineering, Material Science, Chemical Engineering or Physics.
• 2–8 years of fab experience in high‑volume front‑end semiconductor manufacturing.
• Proven experience in defect analysis and yield enhancement.
• Strong interpersonal, communication and leadership abilities.
• Commitment to environmental, health, safety and security (EHSS) standards.

Required skills

• FIB, SEM, EDX, Optical Microscopy
• Brightfield and Darkfield defect inspection tools
• Recipe creation and management
• Defect source analysis and library building
• Wafer quality assurance and control
• Automation of troubleshooting processes